In recent years, there has existed a semiconductor device which, in order to be connected to a circuit formed outside thereof, includes a semiconductor chip having the following structure.
That is, the semiconductor chip has a circuit-forming surface provided with electrode pads, secondary wires, and external connection terminals to which the circuit is connected. Moreover, there exists a semiconductor chip that has such a structure that a secondary wire is so provided between an electrode pad and an external connection terminal as to connect the semiconductor chip to an external circuit.
Conventionally, this type of semiconductor device has been devised in various ways for suppressing electromagnetic interference between a secondary wire and an electronic circuit (hereinafter referred to simply as “electromagnetic interference”). It should be noted that the electromagnetic interference is a phenomenon in which noise (electrostatically induced noise or electromagnetically induced noise) produced when parasitic capacitance formed between a circuit-forming surface and a secondary wire is coupled to an electrical signal is superimposed onto the electronic circuit.
For example, according to a technique disclosed in Patent Document 1 (Japanese Unexamined Patent Application Publication No. 83894/2002 (Tokukai 2002-83894; published on Mar. 22, 2002)), such electromagnetic interference in a semiconductor chip is suppressed by disposing secondary wires so that the secondary wires do not overlap an electronic circuit (analog circuit section) provided on a circuit-forming surface.
However, according to the technique disclosed in Patent Document 1, in order to arrange the secondary wires so that they do not overlap the electronic circuit, it is necessary that secondary wires that conduct different signals be run so as not to intersect with each other. Therefore, the length of a secondary wire becomes very long depending on where it is formed. This may cause problems with delays in electrical signals inputted and outputted via electrode pads.
Further, in the case of disposition of secondary wires that circumvent the electronic circuit, it is necessary to run a large number of secondary wires between a plurality of external connection terminals. Especially, in cases where a plurality of external connection terminals are peripherally disposed, it is necessary to run a large number of secondary wires around the periphery of these electrode pads (i.e., on the edge of the semiconductor chip). Therefore, a plurality of secondary wires may come extremely close to each other depending on where they are formed, or external connection terminals may be placed at extremely narrow pitches. Moreover, this may cause a problem of inability to ensure a wire width appropriate for an electrical current required by the electronic circuit or a problem of deterioration in yield in the step of forming secondary wires.
Further, according to the technique disclosed in Patent Document 1, the proximity of the secondary wires to each other may cause electrical current leakage and crosstalk noise. Furthermore, according to the technique disclosed in Patent Document 1, as the distance between secondary wires shortens, the parasitic capacitance of an insulating layer existing between the secondary wires increases. This may cause wiring delays.
Further, Patent Document 3 (Japanese Unexamined Patent Application Publication No. 303036/2006 (Tokukai 2006-303036; published on Nov. 2, 2006)) discloses a semiconductor device whose sealing resin layer is so provided in an area free of a rewiring layer as to be in a pattern having holes that absorb stress.
However, the semiconductor device disclosed in Patent Document 3 suffers from a problem of high risk of occurrence of chipping in a dicing step.
That is, since the semiconductor device disclosed in Patent Document 3 is merely arranged such that the sealing resin layer is provided with the holes, the semiconductor device disclosed in Patent Document 3 becomes arranged such that an insulating layer having substantially the same thickness as an area provided with a rewiring layer is provided in an area near a scribe line. However, in cases where an insulating layer, or an organic insulating layer in particular, is formed thickly in an area near the scribe line, the formation of the insulating layer alone can be a factor that causes chipping in the dicing step. This is because the chipping is attributed to clogging of a dicing blade. The insulating layer has ductility, and the insulating layer has such properties, for example, that swarf therefrom is prone to adhere to the dicing blade. The formation of the insulating layer in an area near the scribe line causes the semiconductor device to have more incidence of clogging of the dicing blade.
Further, the semiconductor device disclosed in Patent Document 3 suffers from a problem with an increase in the curvature of a wafer.
That is, stress that affects the curvature of a wafer becomes very high in a peripheral portion of a joint surface, i.e., in an area of a semiconductor chip near a scribe line. Therefore, the technique disclosed in Patent Document 3 merely arranged such that the sealing resin layer is provided with the holes has difficulty in bringing about a sufficiently great effect of suppressing the curvature of a wafer. In order to obtain a sufficiently great wafer-curvature suppressing effect with use of the technique disclosed in Patent Document 3, it is conceivable that a large number of such holes are formed. However, the formation of a large number of such holes undesirably complicates the structure of the semiconductor device.
The problem with the curvature of a wafer will be described below in detail.